This application claims priority from Korean Patent Application No. 2001-212, filed on Jan. 3, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device capable of providing wordline voltages used in an external memory device to storing multi-bit data.
To substitute conventional hard disks with flash electrically erasable and programmable read only memories (EEPROMs), very high density and fast programming speeds are required. Flash memory EEPROMs and hard disks are included as mass storage facilities of various electronics products such as digital cameras, personal digital assistants, and other portable computing devices. As EEPROMs are used more frequently as mass storage facilities, the per bit price of EEPROMs drops. Multi-level cells are used to increase in density of the EEPROMs.
A technology for reducing the price of a memory per bit is disclosed in U.S. Pat. No. 6,067,248 entitled NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH SINGLE-BIT AND MULTI-BIT MODES OF OPERATION AND METHOD FOR PERFORMING PROGRAMMING AND READING OPERATIONS THEREIN to Tae-Hwa Yoo.
The nonvolatile semiconductor memory device described in the Yoo patent includes multi-level or multi-bit memory cells. Programmed voltages of the respective memory cells are threshold voltages that can represent 2-bits of information. For example, xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d, and xe2x80x9c11xe2x80x9d correspond to programmed threshold voltages 2.5V, 1.5V, 0.5V, and xe2x88x923V, respectively. Put differently, the programmed cell has one of the four threshold voltages.
The process of detecting a data state for a multi-bit memory cell will be described with reference to FIG. 10. Different level read voltages e.g., Vread1, Vread2, and Vread3, between two threshold voltages are sequentially applied to each gate of memory cells via a wordline connected to a memory cell. Whether a current flows via the memory cell determines the data state of the cell. To detect 2-bit data stored in the memory cell, the determining operation or a read operation is carried out continuously three times during a predetermined sense interval.
To check whether a programmed memory cell has a required data state, a program verify operation is carried out. The verify operation is identical to the read operation except that the voltage levels of the verify voltages Vvfy1, Vvfy2, and Vvfy3 are different from those of the read voltages Vread1, Vread2, and Vread3. In this case, the Vvfy1, Vvfy2, and Vvfy3 are sequentially applied to each gate of the memory cells via a wordline. The verify voltages Vvfy1, Vvfy2, and Vvfy3 are greater than the Vread1, Vread2, and Vread3 by a voltage value corresponding to, for example, a half of a margin between adjacent threshold voltages.
As explained above, in order to read out data stored in a memory cell, a multi-bit nonvolatile semiconductor memory device requires six wordline voltages whose voltage levels are different from each other. To correctly read out the data stored in the memory cell, wordline voltages must be in accord with target values in design. Accordingly, a device capable of measuring and testing wordline voltages whose voltage levels are different from each other, is required.
One way of measuring wordline voltages utilizes a probe device. However, the probe device is not efficient and has difficulty correctly measuring target values because AC voltages are quickly applied to a wordlines during read and verify operations.
Accordingly, a need remains for a nonvolatile semiconductor memory device that directly and accurately measures wordline voltages.
According to one embodiment of the present invention, a semiconductor memory device includes a memory cell array having a plurality of wordlines, a plurality of bitlines, a plurality of memory cells located at intersections of the wordlines and the bitlines. The memory device includes a row selector, a select signal generator, a wordline voltage generator, and a switch circuit. The row selector is coupled to the wordlines. The row selector selects one of the wordlines and supplies a wordline voltage to the selected wordline. During a test operation mode, the select signal generator activates one of the select signals corresponding to the other wordline voltages responsive to an external instruction and external select code signals. The wordline voltage generator generates a wordline voltage corresponding to the activated one of the other wordline voltages. The switch circuit transfers the wordline voltage to a pad responsive to the external instruction signal.
Each of the memory cells stores multi-bit data and has one of a plurality of threshold voltages. The semiconductor memory device further includes a controller for generating an operation interval enable signal representing each operation interval of the test, normal read, and normal verify operation modes. The voltage generator is activated by the operation interval enable signal.
When performing the normal read/verify operations, the controller sequentially generates interval signals for appointing sense intervals for the normal read/verify operations. The select signal generator sequentially activates select signals, each select signal corresponding to sense intervals of the respective read and verify operations responsive to the interval signals. The select signals generated in the read and verify operations correspond to the other wordline voltages. The voltage generator generates a wordline voltage responsive to the activated select signal. Each of the memory cells includes an EEPROM cell. If the semiconductor memory device is packed, the pad is coupled to one of external pins of the packed memory device.
According to another embodiment of the invention, a method of measuring wordline voltages that are applied to a semiconductor memory device is provided. The memory device includes a memory cell array having a plurality of wordlines, a plurality of bitlines, and a plurality of memory cells located at intersections of the wordlines and the bitlines. A row selector selects one of the wordlines and supplies a wordline voltage to the selected wordlines. A wordline voltage generator generates other wordline voltages to be applied to the selected wordline. An external instruction signal is provided to inform a test operation mode. A determination is made of whether the wordline voltage has a required level. An external select code signal is then provided to appoint one of the other wordline voltages. During the test operation mode, one of the select signals is activated responsive to the external select code signal. The wordline voltage generator generates a wordline voltage corresponding to the activated one of the wordline voltages. Finally, the wordline voltage is provided to the semiconductor memory device via a pad depending upon the external instruction signal.